Dr. Esther Rani worked on the research topic of, “Design of Modified Self-Sleep Buffer for Distributed MTCMOS Technique in Arithmetic And Fast Computations”. In her work, four different methods for the design of self sleep circuit had been proposed, implemented and verified in the design of a simple General Purpose Microprocessor and Fast Fourier Transform (FFT) for the optimization of power in standby mode. Whole design has been carried out in 90-nm technology with 2GHz clock frequency using Cadence tools. This has been filed for patent and it was published in ‘The Official Journal of Patent Office’ on 30/05/2013 with the title, “Self Sleep Device For Low Power VLSI Applications”. Dr. Esther Rani also has been awarded the “Research Award” by UGC for the period of two years from Mar’ 2015-Feb’ 2017 with a research grant.